1. Field of the Invention
The field of the present invention is semiconductor devices and manufacture methods, particularly for MOSFET semiconductors.
2. Background
One of the major challenges for CMOS scaling is the increased parasitics that the semiconductors exhibit when reduced to smaller and smaller scales. As one example, as the feature sizes of semiconductor devices continue to shrink, the parasitic capacitance between the source/drain contacts and the gate contact increases. The result is a degradation in the overall performance of the scaled down device.
Another challenge introduced with smaller scale devices is found in the increased aspect ratio of the source/drain contacts, which causes difficulties in forming the contacts using well-known reactive ion etching (RIE) and fill techniques.
Previously, stress liners have been introduced, and also widely adopted, into semiconductor devices to boost device performance by significantly reducing, if not eliminating, the aforementioned parasitic capacitance. However, the effectiveness of stress liner is reduced by the gate stack, which typically has a relatively tall gate stack.